The invention relates to a semiconductor device having a semiconductor body comprising at least an insulated gate field effect transistor having a surface-adjacent first region of a given conductivity type, a surface-adjacent channel region of a first conductivity type surrounded at least laterally by the first region, a source zone of the second opposite conductivity type adjoining the surface and surrounded within the semiconductor body at least in part by the channel region, a surface-adjacent channel zone between the source zone and the first region and forming part of the channel region, a drain zone of the second conductivity type which is separated by a part of the first region--the drift region--from the channel region and has a higher doping concentration than the first region, an electrically insulating layer located at least on the channel zone and a gate electrode located on the insulating layer above the channel zone.
The invention further relates to a method of manufacturing the device.
A semiconductor device of the kind described above is known from U.S. Pat. No. 3,926,694.
With the use of insulated gate field effect transistors, which are often briefly designated as MOS transistors, the mutual conductance or transconductance ##EQU1## where I.sub.D is the drain current, V.sub.g is the gate voltage and V.sub.DS is the voltage between the source zone and the drain zone, is of major importance.
For such field effect transistors, it is desirable in many cases that they can be used at high to very high frequencies, and moreover that even with small currents they have a high mutual conductance g.sub.m and a good linearity, that is to say a minimum variation of g.sub.m with varying V.sub.g.
It is known that a conventional high-frequency insulated gate field effect transistor has not only a better high-frequency behavior, but also a higher mutual conductance and a better linearity as the channel is made shorter. In order to obtain the high value of g.sub.m desired for many applications, a channel length of at most 1 .mu.m is necessary.
Such very short channel lengths can be attained in practice most easily with insulated gate field effect transistors of the so-called DMOST type.In this case, the doping of the source zone and that of the channel region take place through the same window. The lateral dimension of the channel region is then determined by the difference in lateral diffusion of the source zone and of the channel region. Such a field effect transistor has been described in the aforementioned U.S. Pat. No. 3,926,694.
In DMOS transistors, however, a complication occurs due to the fact that the g.sub.m -V.sub.g characteristic is determined not only by the formulation of a "short" channel in the narrow diffused channel region controlled by the signal, but also by the formation--under the influence of the gate electrode--behind this region of a controlled "long" channel in the "drift region" located between the channel region and the drain zone. As a result, at a given value V.sub.go of the gate voltage, a local maximum value g.sub.mo of the mutual conductance occurs; with a further increase of the gate voltage, the mutual conductance decreases again, after which it gradually increases again. This is connected with the fact that with control voltages above V.sub.go, the current is determined not only by the "short" channel, but also by the "long" channel due to the fact that the "short" channel passes from the pinched-off state to the non-pinched-off state. Consequently, an irregularity occurs in the form of a peak in the g.sub.m -V.sub.g characteristic and the mutual conductance g.sub.m remains considerably lower than with a conventional MOS transistor having the same gate electrode structure and a channel length corresponding to the "short" channel of the DMOST.
By varying the ratio of the lengths of the short and the long channel, the height of the said peak and the gate voltage at which it occurs can be varied. It has been found that with an unchanged overall length of the short and the long channel, the height of the peak decreases and consequently the linearity for gate voltages larger than V.sub.go is improved as the lengths of the short and of the long channel approach each other. This linearity, which is even better than with a conventional MOS transistor having a comparable short channel, only occurs, however, at a comparatively high value of the gate voltage V.sub.g and for a comparatively low value of the mutual conductance g.sub.m.